1 ps8765a 08/01/05 product features ? dual differential 3.3v lvpecl outputs ? selectable crystal oscillator interface or lvcmos/lvttl test_clk ? output frequency range: 53.33mhz to 366.67mhz ? crystal input frequency range: 14mhz to 40mhz ? test_clk freqeuncy range: 10mhz to 50mhz ? vco range: 320mhz to 1.1ghz ? parallel or serial interface for programming counter and output dividers ? rms period jitter: 3ps (typical) ? 3.3v supply voltage ? 0c to 70c ambient operating temperature ? packages (pb-free & green available): - 32-pin lqfp (fb) PI6C484321 260mhz crystal-to-3.3v differential lvpecl frequency synthesizer description the PI6C484321 is a dual output, 3.3v lvpecl frequency syn - thesizer using crystal as the input source. the input source is can be selected from either lvttl/lvcmos level input (test_clk pin) or crystal inputs. the vco operates at a frequency range of 320mhz to 1.1ghz. the vco frequency is programmed in steps equal to the value of the input reference or crystal frequency. the vco and output frequency can be programmed through a simple 2-wire serial interface or through 11-bit parallel interface. the low phase noise characteristics of the PI6C484321 make it an ideal clock source for fibre channel 1 (fc1), fibre channel 2 (fc2), 10 gigabit fibre channel (10gfc), gigabit ethernet and 10 gigabit ethernet (10gbe) applications. block diagram pin confguration osc vco_sel xt al_sel test_clk xt al1 xt al2 s_lo ad s_d at a s_clock np_lo ad m0:m8 n0:n1 pll fout0 nfout0 fout1 nfout1 test ? 0 1 0 1 mr m vco phase detect or configura tion interf ac e logic 3 4 5 6 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 xt al2 test_clk xt al_sel v cca s_lo ad s_d at a s_clock mr m5 m6 m7 m8 n0 n1 nc v ee v ee nfout0 fout0 v cco nfout1 fout1 v cc test xt al1 np_lo ad vco_sel m0 m1 m2 m3 m4
2 ps8765a 08/01/05 PI6C484321 260mhz crystal-to-3.3v differential lvpecl frequency synthesizer functional description the following functional description describes operations using a 25mhz crystal. valid pll loop divider values for different crystal or input frequencies are defned in the input frequency characteristics, table 5, note 1. the PI6C484321 features a fully integrated pll, thus requires no external components for setting the loop bandwidth. a funda - mental crystal is the input to the internal oscillator. the output of the oscillator is fed into the phase detector. a 25mhz crystal provides a 25mhz reference frequency to the phase detector. the actual vco range of the pll is 320mhz to 1.1ghz. the output of the m divider is used by the phase detector. the phase detector and the m divider force the vco output frequency to be m times the reference frequency by adjusting the vco control voltage. note that for some illegal values of m (either too high or too low), the pll will not achieve lock. the output of the vco is scaled by a divider prior to being sent to each of the lvpecl output buffers. the divider provides a 50% output duty cycle. the programmable feature that selects the m divider and n out - put divider supports two modes: parallel and serial modes. figure 1 shows the timing diagram for each mode. in parallel mode, the np_load input is initially low. the data on inputs m0 through m8 and n0 and n1 is passed directly to the m divider and n out - put divider. on the low-to-high transition of the np_load input, the data is latched and the m divider remains loaded until the next low transition on np_load or until a serial event oc - curs. as a result, the m and n bits can be hardwired to set the m divider and n output divider to a specifc default state that will automatically occur during power-up. the test output is low when operating in the parallel input mode. the relation - ship between the vco frequency, the crystal frequency and the t1 t0 test output 0 0 low 0 1 s_data 1 0 output of m divider 1 1 cmos fout parallel & serial load operations m divider is defned as follows: fvco = fxtal x m the m value and the required values of m0 through m8 are shown in table 3b to program the vco frequency function table. the output frequency is defned as follows: serial operation occurs when np_load is high and s_load is low. the shift register is loaded by sampling the s_data bits with the rising edge of s_clock. the contents of the shift register are loaded into the m divider and n output divider when s_load transitions from low-to-high. the m divide and n output divide values are latched on the high-to-low transition of s_load. if s_load is held high, data at the s_data in - put is passed directly to the m divider and n output divider on each rising edge of s_clock. the serial mode can be used to program the m and n bits and test bits t1 and t0. the internal registers t0 and t1 determine the state of the test output as follows: fout = fvco = fxtal x m n n time s erial l o ading p arallel l o ading m, n t s t h t s t h t s t 1 t0 * null n1 n0 m8 m7 m6 m5 m4 m3 m2 m1 m 0 s_clock s_da ta s_load np_load m0:m8, n0:n1 np_load
3 ps8765a 08/01/05 PI6C484321 260mhz crystal-to-3.3v differential lvpecl frequency synthesizer pin description number name type description 1 m5 input pullup m divider input. data latched on low-to-high transition of np_ load input. lvcmos / lvttl interface levels 2, 3, 4, 28, 29, 30, 31, 32 m6, m7, m8, m0, m1, m2, m3, m4 input pulldown 5, 6 n0, n1 input pulldown determines n output divider value as defned in table 3c function table. lvcmos / lvttl interface levels 7 nc unused no connect 8, 16 v ee power negative supply pins 9 test output test output. active in the serial mode of operation. output driven low in parallel mode. lvcmos interface levels 10 v cc power positive supply pin 11, 12 fout1, nfout2 output differential output for the synthesizer. lvpecl interface levels 13 v cco power output supply pin 14, 15 fout0, nfout0 output differential output for the synthesizer. lvpecl interface levels 17 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true outputs foutx to go low and the inverted out - puts nfoutx to go high. when logic low, the internal dividers and the outputs are enabled. assertion of mr does not affect loaded m, n, and t values. lvcmos / lvttl interface levels. 18 s_clock input pulldown clocks in serial data present at s_data input into the shift register on the rising edge of s_clock. lvcmos / lvttl interface levels. 19 s_data input pulldown shirft register serial input. data sampled on the rising edge of s_clock. lvcmos / lvttl interface levels. 20 s_load input pulldown control transition of data from shift register into the dividers. lvcmos / lvttl interface levels 21 v cca power analog supply pin 22 xtal_sel input pullup selects between crystals or test inputs as the pll reference source. selects xtal inputs when high. selects test_clk when low. lvcmos / lvttl interface levels. 23 test_clk input pulldown test clock input. lvcmos / lvttl interface levels 24, 25 xtal1, xtal2 input crystal oscillator inputs 26 np_load input pulldown parallel load input to determine when data present at m8:m0 is loaded into m divider, and when data is present at n1:n0 sets the n output divider value. lvcmos / lvttl interface levels. 27 vco_sel input pullup controls the clock synthesizer to be in pll or bypass mode. lvcmos /lvttl interface levels notes 1. pullup and pulldown refer to internal input resistors. see pin characterstics table for typical values.
4 ps8765a 08/01/05 PI6C484321 260mhz crystal-to-3.3v differential lvpecl frequency synthesizer pin characteristics symbol parameter min. typ. max. units c in input capacitance 4 pf r pullup input pullup resistor 51 k? r pulldown input pulldown resistor 51 parallel and serial modes function table inputs conditions mr np_load m n s_load s_clock s_data h x x x x x x reset mode, forces outputs low. l l data data x x x data on m and n input passed directly to the m divider. test output forced low l data data l x x data is latched into input registers and remains loaded until next low transition or until a serial event occurs l h x x l data serial input mode. shift register is loaded with data on s-data on each rising edge of s_clock l h x x l data contents of the shift register are passed to the m divider l h x x l data m divider and n output divider values are latched l h x x l x x parallel or serial input do not affect shift registers l h x x h data s_data passed directly to m divider as it is clocked notes: l = low, h = high, x = don't care, = rising edge, and = falling edge transition programmable vco frequency example based on 25mhz input vco freq. m divider 256 128 64 32 16 8 4 2 1 m8 m7 m6 m5 m4 m3 m2 m1 m0 625 25 0 0 0 0 1 1 0 0 1 650 26 0 0 0 0 1 1 0 1 0 675 27 0 0 0 0 1 1 0 1 1 775 31 0 0 0 0 1 1 1 1 1 programmable output divider functiontable inputs n divider value output frequency (mhz) n1 n0 min. max. 0 0 3 106.67 366.67 0 1 4 80 275 1 0 5 64 220 1 1 6 53.33 183.33 notes: fout_min = fvco_min / n = 320mhz / n fout_max = fvco_max /n = 1100mhz / n
5 ps8765a 08/01/05 PI6C484321 260mhz crystal-to-3.3v differential lvpecl frequency synthesizer notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifcations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may effect product reliability. absolute maximum ratings supply voltage, v cc ............................................................ 4.6v inputs, v i .................................................... -0.5v to v cc + 0.5v outputs, v o (lvpecl) ............................ -0.5v to v ddo + 0.5v outputs, i o (lvcmos) continuous current .......................................................... 50ma surge current ............................................................... .. 100ma package thermal impedance, theta ja ......... 47.9oc/w (0 lfpm) storage temperature, t stg ................................ -65o c to 150oc commonly used confguration function table input output frequency (mhz) crystal (mhz) m divider value n divider value 19.44 32 4 155.52 19.53125 32 4 156.25 25 25 4 156.25 25 25 5 125 25.50 25 3 212.50 25.50 25 4 159.375 25.50 25 6 106.25 38.88 16 4 155.52 20 75 20 83.33
6 ps8765a 08/01/05 PI6C484321 260mhz crystal-to-3.3v differential lvpecl frequency synthesizer lvpecl dc characteristics, v cc = v cca = v cco = 3.3v 5%, t a = 0c to 70c symbol parameter test condition min. typ. max. units v oh output high voltage (1) v cco - 1.4 v cco -1.0 v v ol output low voltage (1) v cco -2.0 v cco -1.7 v swing peak-to-peak output voltage swing 0.6 1.0 notes 1. outputs terminated with 50? to v cc -2v. see parameter measurement section, 3.3v output load test circuit. power supply dc characteristics, v cc = v cca = v cco = 3.3v 5%, ta = 0c to 70c symbol parameter min. typ. max. units v cc positive supply voltage 3.135 3.3 3.465 v v cca analog supply voltage 3.135 3.3 3.465 v cco output supply voltage 3.135 3.3 3.465 i ee power supply current 180 ma i cca analog supply current 30 lvcmos / lvttl dc characteristics, v cc = v cca = v cco = 3.3v 5%, ta = 0c to 70c symbol parameter test condition min. typ. max. units v ih input high voltage vco_sel, xtal_sel, mr, s_load, np_load, n0:n1, s_data, s_clock, m0:m8 2 v cc +0.3v v test_clk 2 v cc +0.3v v il input low voltage vco_sel, xtal_sel, mr, s_load, np_load, n0:n1, s_data, s_clock, m0:m8 -0.3 0.8 test_clk -0.3 1.3 i ih input high current m0-m4, m6-m8, n0, n1, mr, s_clock, test_clk, s_data, s_load, np_load v cc = v in = 3.465v 150 a m5, xtal_sel, vco_sel v cc = v in = 3.465v 5 i il input low current m0-m4, m6-m8, n0, n1, mr, s_clock, test_clk, s_data, s_load, np_load v cc = 3.465v, v in = 0v -5 m5, xtal_sel, vco_sel v cc = 3.465v, v in = 0v -150 v oh output high voltage test (1) 2.6 v v ol output low voltage test (1) 0.5 notes 1. outputs terminated with 50? to v cc /2. see parameters measurement information table, 3.3v output load test circuit figure.
7 ps8765a 08/01/05 PI6C484321 260mhz crystal-to-3.3v differential lvpecl frequency synthesizer ac characteristics, v cc = v cca = v cco = 3.3v 5%, t a = 0c to 70c symbol parameter test condition min. typ. max. units f out output frequency 103.3 260 mhz tjit(per) period jitter, rms (1, 3) 3 5 ps tsk(o) output skew(2, 3) 15 ps t r output rise time 20% to 80% 200 700 ps t f output fall time 20% to 80% 200 700 t s setup time mx, nx to np_load 5 ns s_data to s_clock 5 s_clock to s_load 5 t h hold time mx, nx to np_load 5 s_data to s_clock 5 s_clock to s_load 5 odc 45 55 % t lock pll lock time 1 ms notes: 1. jitter performance using xtal inputs. 2. defned as skew between outputs with the same supply voltage and with equal load conditions. measured at the output differential cross points. 3. this parameter is defned in accordance with jedec standard 65 input frequency characteristics , v cc = v cca = v cco = 3.3v5%, t a 0c to 70c symbol parameter test condition min. typ. max. units f in input frequency test_clk (1) 14 40 mhz xtal, xtal2 (1) 14 40 s_clock 50 notes 1. for the input crystal and test_clk frequency range, the m value must be set for the vco to operate with in the 200mhz to 700mhz range. using minimum input frequency of 12mhz, valid values of m are 17 m 58. using the maximun frequency of 25mhz, valid values of m are 8 m 28. crystal characteristics parameter test condition min. typ. max. units mode of oscillation fundamental frequency 14 40 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7 pf
8 ps8765a 08/01/05 PI6C484321 260mhz crystal-to-3.3v differential lvpecl frequency synthesizer paramater measurement information 3.3v output load test circuit scope qx nqx l vpecl 2v -1.3v 0.165v v cc , v cc a , v cco v ee t sk ( o ) nfoutx foutx nfout y fout y v oh v re f v ol mean pe r iod (first ed g e after tr i gg er) ref erence p oint (t r igger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histog ra m pulse width t period t pw t period odc = foutx nfoutx cloc k outputs 20% 80% 80% 20% t r t f v sw i n g output skew output duty cycle/pulse width/period period jitter output rise/fall time
9 ps8765a 08/01/05 PI6C484321 260mhz crystal-to-3.3v differential lvpecl frequency synthesizer packaging mechanical: 32-pin lqfp (fb) seating plane 0.80 bsc .032 0.30 0.45 .012 .018 1.60 .063 1.35 1.45 .053 .057 x.xx x.xx denotes dimensions in millimeters 9.00 bsc .276 square 7.00 bsc .354 square gauge plane 1.00 ref .039 0.45 0.75 .018 .030 0.09 0.20 .004 .008 0 7 0.25 mm max . 0.10 .004 0.05 0.15 .002 .006 ordering information ordering code package code packagetype PI6C484321fb fb 32-pin lqfp PI6C484321fbe fb pb-free & reen, 32-pin lqfp notes: 1. thermal characteristics can be found on the company web site at http://www .pericom.com/packaging/ pericom semiconductor corporation 1-800-435-2336 http://www.pericom.com
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